The present invention relates to an electronic device, and more particularly, to a signal amplifying apparatus.
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional operating amplifier 10. The prior art operating amplifier 10 comprises an input differential stage 11 and an output stage 12. In brief, transistors Ma-Me form the input differential stage 11, and transistors Mf-Mg form the output stage 12. According to the related art, the operating amplifier 10 has a dominant pole, two complex high frequency poles, and a zero. Due to the feed-forward path, which is formed by compensation resistor Rz and compensation capacitor Cc, with no inversion from the input differential stage 11 to the output stage 12 at high frequency, the performance of the operating amplifier displays two degradations. The first is severe degradation of the operating amplifier 10 for capacitive loads CL of the same order as compensation capacitor Cc. The second is the negative power supply VBB displaying a zero at the dominant pole frequency of the operating amplifier 10 in unity gain configuration due to the PMOS transistors in the input differential stage 11. This results in serious performance degradation for sampled data systems that use high-frequency switching regulators to generate their power supplies.
Please refer to FIG. 2. FIG. 2 is a diagram illustrating another conventional operating amplifier 20. The operating amplifier 20 comprises an input differential stage 21, a current transformer 22, and an output stage 23. The input differential stage 21 formed by transistors Ma′-Me′ uses cascade devices Mc1-Mc2 to reduce supply capacitance from the negative power supply VBB for switched-capacitor applications. The current transformer 22 is formed by Mh′-Mj′, in which the technique has been referred to as the “grounded gate cascade compensation”. The output stage 23 is formed by Mf′-Mg′. Compared with the operating amplifier 10 shown in FIG. 1, the operating amplifier 20 provides a virtual ground at node N1 to eliminate the feed-forward path but still produces a dominant pole due to the Miller effect. Therefore, the compensation capacitor Cc′ is connected between the output node N2 and a virtual ground at N1. When designing a high-bandwidth operating amplifier, however, the operating amplifier 20 usually suffers from pole-zero doublet near unity-gain frequency. This is because the pole-zero doublet in the amplifier's unity-gain bandwidth elongates the amplifier's settling time, and consequently limits the amplifier's high-speed performance.